
PIC18F45J10 FAMILY
DS39682E-page 168
2009 Microchip Technology Inc.
FIGURE 16-9:
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING)
SDA
x
SCL
x
BF
(
SSP
xS
TA
T
<
0
>
)
A6
A5
A4
A3
A2
A1
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
S
P
xB
U
F
is
w
rit
te
nin
so
ftw
ar
e
C
leared
in
softw
are
Data
in
sam
pled
S
ACK
Tr
an
sm
itt
ing
D
at
a
R/
W
=
0
ACK
R
ecei
vi
ng
A
ddres
s
A7
D7
9
1
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
SS
Px
B
U
F
is
wr
itt
en
in
s
of
twa
re
C
leared
in
softw
are
Fr
om
SS
Px
IF
IS
R
T
ransmi
tti
ng
D
ata
D7
1
CK
P
(
S
SPx
C
O
N<
4>
)
P
ACK
C
K
P
is
s
et
in
so
ftw
ar
e
C
K
P
is
s
et
in
so
ftw
ar
e
S
C
Lx
hel
dl
ow
wh
ile
CPU
responds
to
S
P
xIF
S
P
xIF
(P
IR
1<
3>
or
P
IR
3
<
7
>
)
F
ro
m
SSPx
IF
IS
R
C
lea
rby
readi
ng